An electronic computer aided design (“E-CAD”) tool is utilized to construct a Very Large Scale Integration (“VLSI”) circuit design. The VLSI circuit design consists of a netlist that identifies electronic design elements (e.g., capacitors, transistors, resistors, etc.) and their interconnectivity (e.g., signal nets) within the VLSI circuit design. A significant characteristic of VLSI and other types of circuit design is a reliance on hierarchical description. A primary reason for using hierarchical description is to hide the vast amount of detail in a design. By reducing the distracting detail to a single object that is lower in the hierarchy, one can greatly simplify many E-CAD operations. For example, simulation, verification, design-rule checking, and layout constraints can all benefit from hierarchical representation, which makes them more computationally tractable. Since many circuit designs are too complicated to be easily considered in their totality, a complete design is often viewed as a collection of design element aggregates that are further divided into sub-aggregates in a recursive and hierarchical manner. In VLSI circuit design, these aggregates are commonly referred to as design blocks or cells. The use of a cell at a given level of hierarchy is called an ‘instance’. Each cell has one or more ‘ports’, each of which provides a connection point between a signal net within the cell and a signal net external to the cell.
A signal net is a single electrical path in a circuit design that has the same electrical characteristics at all of its points. Any collection of wires that carries the same signal between design elements is a signal net. If the design elements allow the signal to pass through unaltered (as in the case of a terminal), then the signal net continues on subsequently connected wires. If, however, the design element modifies the signal (as in the case of a transistor or logic gate), then the signal net terminates at that design element and a signal new net begins on the other side. Connectivity in a circuit design is typically specified using a netlist, which indicates the specific nets that interconnect the various design elements.
A signal net may be divided into signal net ‘pieces’, each of which is part of a Highest Level Signal Name (“HLSN”). A HLSN is the unique signal name that identifies a collection of signal nets or ‘hierarchical signal net pieces’, which are the small pieces of intermediate wire (signal nets) in each hierarchical design block of a circuit design.
A design engineer uses the E-CAD tool to analyze the VLSI circuit design during development. The E-CAD tool typically selects a sub-circuit (known as a ‘stage’) within the circuit design for analysis. Each stage in the circuit design may have instantiation-specific configuration information (e.g., switching frequencies, activity factors and scaling factors of the design elements) that is used by the E-CAD tool during analysis of the stage. For example, the E-CAD tool may sum certain information (e.g., FET size, current, capacitance, or wire width) and utilize the instantiation-specific configuration information to determine overall analysis result.
FIG. 1 shows one exemplary stage 10 that includes two driver FETs 12 and 14, two receiver FETs 26 and 28, three control signal nets A, B, I, and one output signal net C. Stage 10 is used in the following example to illustrate switching current and drive fight.
Source terminals of driver FETs 12, 26 connect to power rail Voltage-Drain-Drain (VDD) by a signal net 16. A drain terminal of FET 12 connects to a source terminal of driver FET 14, and to gate terminals of receiver FETs 26 and 28 by control signal net I. Drain terminals of driver FET 14 and receiver FET 28 connect to a ground power rail (GND) by signal net 18. Control signal net A connects to a gate terminal of FET 12 and control signal net B connects to a gate terminal of driver FET 14. Receiver FETs 26 and 28 are connected to operate as an inverter that inverts control signal I to drive output signal O.
In an exemplary analysis of stage 10, current through receiver FETs 26 and 28 are not included during current simulations of stage 10. Nonetheless, FETs 26 and 28 create capacitive load on control signal I; this capacitive load is illustratively represented by a capacitor COUT shown connected between control signal I and GND. When control signal net A is low and control signal B is high, driver FET 12 is turned off, driver FET 14 is turned on, and control signal I is pulled to GND, thereby discharging capacitance COUT through driver FET 14 (i.e., control signal I is at GND potential). When control signal A is high and control signal B is low, driver FET 14 is turned off and driver FET 12 is turned on, pulling control signal I to VDD, thereby charging capacitor COUT through driver FET 12 (i.e., control signal I is at VDD potential). Each transition of control signal I between GND and VDD draws current from VDD through driver FET 12 to charge capacitor COUT. Each transition of control signal I between VDD and GND sinks current to GND through driver FET 14. These currents are thus known as ‘switching’ current since they derive from control signal I switching states.
If a control signal does not switch states, it is known as a ‘tied’ signal (e.g., the control signal may be ‘tied’ high or low). Where a control signal for a driver FET (e.g., driver FETs 12 and 14) is tied, the driver FET remains either on or off, and is known as a ‘tied’ FET. If all driver FETs within a stage are tied FETs, the stage is known as a ‘tied’ stage and draws zero switching current.
If a signal is driven by two FETs, and one FET attempts to pull the signal to VDD and the other FET attempts to pull the signal to GND, a situation known as ‘drive fight’ occurs. For example, in stage 10, drive fight occurs when driver FET 12 and driver FET 14 are simultaneously turned on (e.g., input A and input B are both high). Control signal I is then simultaneously pulled high, by driver FET 12, and pulled low, by driver FET 14, causing current to flow continuously between power rail VDD and power rail GND through driver FETs 12 and 14.
If input A is tied high and input B is tied low, stage 10 is a tied stage with no drive fight, and thus draws zero current. Similarly, if input A is tied low and input B is tied high, stage 10 is a tied stage with no drive fight, and thus draws zero current. Even though no current is drawn, the E-CAD tool still performs time consuming detailed analyses of stage 10 to determine this zero current situation.
If the VLSI circuit design has billions of design elements, such analyses can take hours or even days of processing time to complete, resulting in lost productivity. Lost productivity due to lengthy engineering development slows technology advancement and can result in significant costs, as well as lost business.